The present invention relates to an integrate and fold circuit used in an analog to digital conversion circuit, and more particularly to an integrate and fold circuit for converting an analog input signal of a digital x-ray and/or computed-tomography (CT) system into digital output bits.
Conventional analog to digital conversion circuits typically include charge to voltage converters that typically comprise an operational amplifier with an integrating capacitor connected between an inverting terminal and an output terminal of the operational amplifier. A linear relationship exits between the input charge (Qin) and the output voltage (Vout) of the operational amplifier when the operational amplifier operates within a characteristic active region. The linear relationship between the input charge (Qin) and the output voltage (Vout) of the operational amplifier is represented as follows:
Qin=Cintxc2x7Vout;
where Qin is the input charge in coulombs; Cint is the capacitance of the integrating capacitor in farads; and Vout is the output voltage of the operational amplifier in volts. Characteristically, the operational amplifier can hold a finite amount of charge before the operational amplifier saturates and begins to display a non-linear relationship between the input charge (Qin) and the output voltage (Vout).
In analog to digital conversion circuits, linear operation of the operational amplifier is desired to accurately resolve the analog input signal into digital output bits. However, to accommodate a large range of input charges (Qin), conventional analog to digital conversion circuits include a capacitor bank containing a plurality of integration capacitors. During operation, one of the plurality of integration capacitors is chosen based on the level of the input charge (Qin) such that the integration amplifier does not saturate and the linear relationship between the input charge (Qin) and the output voltage (Vout) is maintained.
In many applications, it is desired that the analog to digital conversion circuit be integrated in a circuit die. However, the bank of the plurality of integration capacitors requires a large portion of die area. As such, an integrated circuit containing a plurality of integration capacitors occupies a large area on the die and, therefore, increases the cost of each analog to digital conversion circuit. It is desired to have the charge to voltage converter of the analog to digital conversion circuit operate in the active region of the operational amplifier when resolving the analog input signal into digital output bits. In addition, it is desired that a small capacitor be used in the charge to voltage converter so that the analog to digital conversion circuit occupies less area when integrated on a circuit die.
In other applications, the analog to digital conversion circuit is designed so that the power supply voltage is as low as possible such that the power consumption of the circuit is reduced. These systems with lower power supply voltages also have lower input charges (Qin) to the operational amplifier. Therefore, the integration capacitor (Cint) is designed to be large in order to maintain a large output voltage (Vout) range. As explained above, large integration capacitors occupy large die areas when integrated into a circuit die, and, as such, the cost per analog to digital conversion circuit is increased. Therefore, it is desired to have an analog to digital conversion circuit that comprises a small capacitor such that a smaller die area is required for an integrated circuit, and further such that the small capacitor also maintains a relatively large output voltage (Vout) range.
In conventional analog to digital conversion circuits, the output voltage (Vout) is constrained to only half of the dynamic range of the power supply voltage when the input charge (Qin) is fixed. For example, in conventional circuits, when the direction of the current flow of the input charge (Qin) is fixed, the output voltage (Vout) will increase from analog ground to positive power supply voltage. Therefore, only the positive half of the power supply voltage range (from zero to positive power supply voltage) is used, and the negative half (from zero to negative power supply voltage) is not used. For conventional analog to digital conversion circuits to use the full dynamic range of the power supply voltage, level-shifting circuitry is required. This level-shifting circuitry also occupies valuable integrated circuit die space and can introduce delays in the analog to digital conversion. Therefore, an analog to digital conversion circuit is desired that used uses the full dynamic range of the power supply voltage without the use of level-shifting circuitry.
In one exemplary embodiment of the present invention, an analog to digital conversion circuit is provided for converting an analog input signal into a plurality of binary output bits. The analog to digital conversion circuit includes an operational amplifier having an inverting terminal and an output terminal, and the analog input signal being connected to the inverting terminal. An integrating capacitor is connected between the inverting terminal and the output of the operational amplifier. The integrating capacitor stores a charge proportional to the integral of the input signal. A charge subtracting circuit is selectively coupled to the inverting terminal and the output of the operational amplifier. The charge subtracting circuit removes a first predetermined charge from the integrating capacitor when an output charge of the operational amplifier is substantially equal to a second predetermined charge. The first predetermined charge is removed from the integrating capacitor a number of times. The removal of the first predetermined charge a number of times allows the integral of the analog input signal to be larger than a maximum charge capable of being stored by the integrating capacitor.
A digital logic circuit is connected to the charge subtracting circuit. The digital logic circuit tracks the number of times that the first predetermined charge is removed from the integrating capacitor by the charge subtracting circuit, and the digital logic circuit provides at least one bit of the plurality of binary output bits. A residue quantizing circuit is connected to the integrating capacitor and the output of the operational amplifier. The residue quantizing circuit determines a residual charge in the integrating capacitor and provides at least one additional bit of the plurality of binary output bits corresponding to the residual charge. The residual charge is substantially equal to the stored charge in the integrating capacitor after the first predetermined charge has been removed from the integrating capacitor a number of times. A low pass filter circuit is selectively coupled to the output of the operational amplifier when the number of times that the first predetermined charge is removed from the integrating capacitor is less than a predetermined number.
In another embodiment, the residue quantizing circuit includes a plurality of integrate and fold circuits. Each of the integrate and fold circuits are connected in a pipeline series configuration and include a sample and hold circuit connected to an output of a preceding integrate and fold circuit for receiving an integrate and fold residual charge. A first of the plurality of integrate and fold circuits is connected to the integrating capacitor and the output of the operational amplifier to receive the residual charge in the integrating capacitor. An integrate and fold operational amplifier has an inverting terminal and an output terminal, and the sample and hold circuit is connected to the inverting terminal of the integrate and fold operational amplifier. An integrate and fold integrating capacitor is connected between the inverting terminal and the output of the integrate and fold operational amplifier. The integrate and fold integrating capacitor stores an integrate and fold charge level proportional to the integral of the integrate and fold residual charge from the preceding integrate and fold circuit. An integrate and fold charge subtracting circuit is selectively coupled to the inverting terminal and the output of the integrate and fold operational amplifier. The integrate and fold charge subtracting circuit removes a first integrate and fold predetermined charge from the integrate and fold integrating capacitor when an output charge of the integrate and fold operational amplifier is substantially equal to a second integrate and fold predetermined charge. The first integrate and fold predetermined charge is removed from said integrate and fold integrating capacitor a number of times. An integrate and fold digital logic circuit is connected to the integrate and fold charge subtracting circuit and tracks the number of times that the first integrate and fold predetermined charge is removed from the integrate and fold integrating capacitor by the integrate and fold charge subtracting circuit. The integrate and fold digital logic circuit provides the at least one additional bit of the plurality of binary output bits.